1. Field of the Invention
The present invention relates to beam lithography. More specifically, the present invention relates to procedures and materials for the reduction of charging during e-beam, ion beam, and X-ray lithography.
2. Description of the Related Art
Electron-beam lithography is a process whereby a pattern is written or printed into an imaging layer on a substrate using an electron exposure source. The substrate may be a surface on which a device or material will be directly patterned or it may be a surface which will eventually be used as a mask or mold in a subsequent patterning procedure. The susceptibility of the imaging layer to electron irradiation allows the chemistry and/or surface energy of the layer to be modified upon electron exposure. Selective exposure of the imaging layer by scanning the e-beam can be used to create a patterned chemical template on the surface. Typically the imaging layer is a polymer, known as a resist, whose chemistry is altered by electron exposure. The chemical change leads to a change in solubility of the polymer in a particular solution, known as the developer. This allows for selective removal of the irradiated (or unirradiated) regions of the layer. The pattern may be transferred into the underlying substrate by a variety of processes such as, but not limited to, selective etching or materials deposition on or in the imaging layer pattern. This process is routinely used to fabricate electronic devices and lithographic masks. Other U.S. applications include, for example, the fabrication of encryption messages on surfaces. The treasury department has investigated the possibility of writing e-beam patterns on currency to reduce the ease of counterfeiting. It is intended that the invention cover these novel applications as well as the more common applications in mask making, semiconductor device manufacture, electro-optic device manufacturing, micro-electromechanical (MEMs) device manufacturing, system on a chip (SOC), and data storage.
In e-beam lithography, charging of the substrate-resist system can occur. The resulting electric field can deflect the e-beam causing pattern placement and critical dimension (CD) error. The international Semiconductor Industry Association (SIA) has constructed a roadmap for projected specifications for semiconductor devices, mandated by economic drivers. By the end of the next decade a pattern placement accuracy of  less than 20 nm and a CD tolerance of  less than 5 nm will be required. Other industries, such as data storage, are on similar roadmaps. Consequently, pattern placement errors due to charging in e-beam lithography are becoming an increasingly important problem.
Charging, in e-beam lithography, originates when the number of electrons entering a region of a material does not equal the number of electrons exiting that region of material. Conditions encountered in e-beam lithography typically fall into one of the following three categories: I) lithography on an insulating substrate, II) lithography of an insulating layer on a conducting substrate with no or only partial penetration of the beam to the substrate, and III) lithography of an insulating layer on a conducting substrate, with full penetration of the beam to the conducting substrate. These cases are illustrated in FIGS. 1a-1c, respectively. As shown in FIG. 1a, under electron irradiation 10 of an insulator 12, a charge density builds until eventually the resulting voltage exceeds the dielectric breakdown of the material and media between the material and ground. At this point, discharge occurs via conduction to the ground. This form of charge buildup and dissipation in e-beam lithography is highly undesirable. Very large electric fields are attained and the fields change unpredictably with time. For example, under these conditions we have measured voltages in excess of 100 V. In reality, the dielectric breakdown is determined by poorly defined and uncontrolled defects in the materials system. In Case III, the beam 10 penetrates the insulating layer 12 to the conducting substrate 16. Here, a small surface potential can develop due to the emission of secondary electrons 18 from the surface. Under these conditions we have measured surface potentials of magnitudes 2-10 V. In between the two extremes is Case II, that of an insulating layer on a conducting substrate with no or partial penetration of the insulating layer by the electron beam. If there is no penetration of the beam to the conducting substrate then the results are equivalent to those of Case I. If there is partial penetration of the beam we have found that electron-beam induced current (EBIC) effects are substantial. Penetration of as little as 25% of the beam to the conductor can lead to sufficient conductivity to dissipate any building charge, in which case the results are equivalent to Case III.
The same charging concerns are present for ion beam and X-ray lithography.
An important technological example of Case I is encountered in the manufacture of phase shift masks and optical devices on glass or quartz substrates. An example of Case II is encountered in low voltage e-beam lithography, such as with the low voltage micro-machined e-beam column arrays currently under development at ETEC, Inc. Most often, one uses a bilayer resist scheme for patterning in which the beam penetrates the top resist layer and the developed pattern is etched into an underlying polymer or dielectric layer. Case III is typically encountered with the low voltage e-beam lithography of thin, single layer resist systems, and higher e-beam voltage machines. The deflection of the e-beam due to sample charging will be most pronounced with the lower voltage and or greater working distance e-beam instruments.
Accordingly, it is an object of the present invention to provide a method of making an anti-charging layer for beam lithography (including electron beam, ion beam, and X-ray lithography) and mask fabrication.
Additional objects and advantages of the invention will be set forth in the description which follows, and, in part, will be obvious from the description, or may be learned by practice of the invention.
Objects of the present invention are achieved by applying a metal ligating self-assembled monolayer to a substrate, binding a metal to the ligand site of the metal ligating self-assembled monolayer and applying a resist to the metal.
According to one aspect of the present invention, there is provided a method of forming anti-charging layer for charged particle beam lithography, comprising binding a ligand self-assembled monolayer (SAM) to a substrate; binding a Pd catalyst to the ligand SAM; depositing an electroless metal layer on the Pd catalyst in order to create the anti-charging layer, the metal layer being continuous and conductive in order to permit charge dissipation, the metal layer being further transparent in the visible region; and coating the anti-charging layer with an imaging resist.
In another aspect, the present invention provides a method of forming an anti-charging layer for charged particle beam lithography, comprising applying an imaging resist to a substrate; binding a ligand to the imaging resist; binding a Pd catalyst to the ligand; and depositing an electroless metal layer onto the Pd catalyst in order to create the anti-charge layer, the metal layer being continuous and conductive in order to permit charge dissipation, the metal layer being further transparent in the visible region.
In a further aspect, there is provided a method for forming an anti-charging layer for charged-particle beam lithography, comprising i) binding a first ligand layer to a substrate; ii) binding a catalyst to the first ligand layer; iii) depositing an electroless metal anticharging layer on the catalyst, the metal anticharging layer being continuous and conductive in order to permit charge dissipation, the metal anticharging layer being further transparent in the visible region; iv) applying a polymer imaging resist layer on the anticharging layer; v) depositing a second ligand layer on the polymer imaging resist; vi) binding a catalyst to the second ligand layer; and vii) depositing an electroless metal anticharging layer on the catalyst in step vi.
The technique can be carried out on a non-patterned surface, a patterned surface, or a planarizer. The resist can be a self-assembled monolayer film or a composite self-assembled monolayer film.